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copyright ? alliance semiconductor. all rights reserved. ? as4c4m4f1 5v 4m4 cmos dram (fast page mode) 5/22/01; v.1.2 alliance semiconductor p. 1 of 13 may 2001 features ? organization: 4,194,304 words 4 bits high speed - 50/60 ns ras access time - 25/30 ns column address access time - 12/15 ns cas access time low power consumption - active: 908 mw max - standby: 5.5 mw max, cmos i/o fast page mode refresh - 2048 refresh cycles, 32 ms refresh interval for as4c4m4f1 -ras -only or cas -before-ras refresh ttl-compatible, three-state i/o jedec standard package - 300 mil, 24/26-pin soj - 300 mil, 24/26-pin tsop latch-up current 200 ma esd protection 2000 volts industrial and commercial temperature available pin arrangement a8 a7 a6 a5 a4 a10 a0 a1 a2 a3 v cc gnd gnd i/o3 i/o2 cas oe v cc i/o0 i/o1 we ras 1 2 3 4 5 26 25 24 23 22 nc a9 621 8 9 10 11 18 17 16 15 14 12 soj as4c4m4f1 a8 a7 a6 a5 a4 a10 a0 a1 a2 a3 v cc gnd gnd i/o3 i/o2 cas oe v cc i/o0 i/o1 we ras 1 2 3 4 5 nc a9 6 tsop as4c4m4f1 13 19 pin designation pin(s) description a0 to a10 address inputs ras row address strobe cas column address strobe we write enable i/o0 to i/o3 input/output oe output enable v cc power gnd ground selection guide symbol as4c4m4f1-50 as4c4m4f1-60 unit maximum ras access time t rac 50 60 ns maximum column address access time t caa 25 30 ns maximum cas access time t cac 12 15 ns maximum output enable (oe ) access time t oea 13 15 ns minimum read or write cycle time t rc 85 100 ns minimum fast page mode cycle time t pc 25 30 ns maximum operating current i cc1 135 120 ma maximum cmos standby current i cc5 2.0 2.0 ma 8 9 10 11 12 13 18 17 16 15 14 19 26 25 24 23 22 21
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 2 of 13 ? functional description the as4c4m4f1 is a high performance 16-megabit cmos dynamic random access memory (dram) device organized as 4,194,304 words 4 bits. the device is fabricated using advanced cmos technology and innovative design techniques resulting in high speed, ext remely low power and wide operating margins at component and system levels. the alliance 16mb dram family is optimized for use as main mem ory in pc, workstation, router and switch applications. this device features a high speed page mode operation where read and write operations within a single row (or page) can be exec uted at very high speed by toggling column addresses within that row. row and column addresses are alternately latched into input buffe rs using the falling edge of ras and cas inputs respectively. also, ras is used to make the column address latch transparent, enabling application of column addresses prior to cas assertion. refresh on the 2048 address combinations of a0 to a10 must be performed every 32 ms using: ras -only refresh: ras is asserted while cas is held high. each of the 2048 rows must be strobed. outputs remain high impedence. hidden refresh: cas is held low while ras is toggled. refresh address is generated internally. outputs remain low impedence with previous valid data. cas -before-ras refresh (cbr): cas is asserted prior to ras . refresh address is generated internally. outputs are high-impedence (oe and we are don't care). normal read or write cycles refresh the row being accessed. the as4c4m4f1 is available in the standard 24/26-pin plastic soj and 24/26-pin plastic tsop packages. the as4c4m4f1 operates wi th a single power supply of 5v 0.5v and provides ttl compatible inputs and outputs. logic block diagram for 2k refresh recommended operating conditions ? v il min -3.0v for pulse widths less than 5 ns. recommended operating conditions apply throughout this document unlesss otherwise s pecified. parameter symbol min nominal max unit supply voltage v cc 4.5 5.0 5.5 v gnd 0.0 0.0 0.0 v input voltage v ih 2.4 ? v cc v v il ?0.5 ? ?0.8v ambient operating temperature commercial t a 0?70 c industrial -40 ? 85 ras clock generator refresh controller 2048 2048 4 array (16,777,216) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd address buffers a8 row decoder column decoder substrate bias generator data i/o buffers oe ras cas we clock generator we i/o0 to i/o3 cas clock generator a9 a10
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 3 of 13 ? absolute maximum ratings dc electrical characteristics parameter symbol min max unit input voltage v in -1.0 +7.0 v input voltage (dqs) v dq -1.0 v cc + 0.5 v power supply voltage v cc -1.0 +7.0 v storage temperature (plastic) t stg -55 +150 c soldering temperature time t solder ? 260 10 o c sec power dissipation p d ?1w short circuit output current i out ?50ma parameter symbol test conditions -50 -60 unit notes min max min max input leakage current i il 0v v in +5.5v, pins not under test = 0v -5 +5 -5 +5 a output leakage current i ol d out disabled, 0v v out +5.5v -5+5-5+5a operating power supply current i cc1 ras , cas address cycling; t rc =min ? 135 ? 120 ma 1,2 ttl standby power supply current i cc2 ras = cas v ih ? 2.0 ? 2.0 ma average power supply current, ras refresh mode or cbr i cc3 ras cycling, cas v ih , t rc = min of ras low after cas low. ? 120 ? 110 ma 1 fast page mode average power supply current i cc4 ras = v il , cas, address cycling: t hpc = min ? 130 ? 120 ma 1, 2 cmos standby power supply current i cc5 ras = cas = v cc - 0.2v ? 2.0 ? 2.0 ma output voltage v oh i out = -5.0 ma 2.4 ? 2.4 ? v v ol i out = 4.2 ma ? 0.4 ? 0.4 v cas before ras refresh current i cc6 ras , cas cycling, t rc = min ? 120 ? 110 ma
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 4 of 13 ? ac parameters common to all waveforms read cycle symbol parameter -50 -60 unit notes minmaxminmax t rc random read or write cycle time 80 ? 100 ? ns t rp ras precharge time 30 ? 40 ? ns t ras ras pulse width 50 10k 60 10k ns t cas cas pulse width 8 10k 10 10k ns t rcd ras to cas delay time 15 35 15 43 ns 6 t rad ras to column address delay time 12 25 12 30 ns 7 t rsh cas to ras hold time 10 ? 10 ? ns t csh ras to cas hold time 40 ? 50 ? ns t crp cas to ras precharge time 5 ? 5 ? ns t asr row address setup time 0 ? 0 ? ns t rah row address hold time 8 ? 10 ? ns t t transition time (rise and fall) 1 50 1 50 ns 4,5 t ref refresh period ? 32 ? 32 ms 16 t cp cas precharge time 8 ? 10 ? ns t ral column address to ras lead time 25 ? 30 ? ns t asc column address setup time 0 ? 0 ? ns t cah column address hold time 8 10 ? ns symbol parameter -50 -60 unit notes min max min max t rac access time from ras ? 50 ? 60 ns 6 t cac access time from cas ? 12 ? 15 ns 6,13 t aa access time from address ? 25 ? 30 ns 7,13 t rcs read command setup time 0 ? 0 ? ns t rch read command hold time to cas 0?0?ns9 t rrh read command hold time to ras 0?0?ns9
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 5 of 13 ? write cycle read-modify-write cycle refresh cycle symbol parameter -50 -60 unit notes min max min max t wcs write command setup time 0 ? 0 ? ns 11 t wch write command hold time 10 ? 10 ? ns 11 t wp write command pulse width 10 ? 10 ? ns t rw l write command to ras lead time 10 ? 10 ? ns t cwl write command to cas lead time 8 ? 10 ? ns t ds data-in setup time 0 ? 0 ? ns 12 t dh data-in hold time 8 ? 10 ? ns 12 symbol parameter -50 -60 unit notes min max min max t rw c read-write cycle time 113 ? 135 ? ns t rw d ras to we delay time 67 ? 77 ? ns 11 t cwd cas to we delay time 32 ? 35 ? ns 11 t aw d column address to we delay time 42 ? 47 ? ns 11 symbol parameter -50 -60 unit notes min max min max t csr cas setup time (cas -before-ras )5?5?ns3 t chr cas hold time (cas -before-ras )8?10?ns3 t rpc ras precharge to cas hold time 0 ? 0 ? ns t cpt cas precharge time (cbr counter test) 10 10 ? ns
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 6 of 13 ? fast page mode cycle output enable symbol parameter -50 -60 unit notes min max min max t cpa access time from cas precharge ? 28 ? 35 ns 13 t rasp ras pulse width 50 100k 60 100k ns t pc read-write cycle time 30 ? 35 ? ns t cp cas precharge time (fast page) 10 ? 10 ? ns t pcm fast page mode rmw cycle 80 ? 85 ? ns t crw page mode cas pulse width (rmw) 12 ? 15 ? ns symbol parameter -50 -60 unit notes min max min max t clz cas to output in low z 0 ? 0 ? ns 8 t roh ras hold time referenced to oe 8?10?ns t oea oe access time ? 13 ? 15 ns t oed oe to data delay 13 ? 15 ? ns t oez output buffer turnoff delay from oe 013015ns8 t oeh oe command hold time 10 ? 10 ? ns t olz oe to output in low z 0 ? 0 ? ns t off output buffer turn-off time 0 13 0 15 ns 8,10
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 7 of 13 ? notes 1i cc1 , i cc3 , i cc4 , and i cc6 are dependent on frequency. 2i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 3 an initial pause of 200 s is required after power-up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 ac characteristics assume t t = 2 ns. all ac parameters are measured with a load equivalent to two ttl loads and 100 pf, v il (min) gnd and v ih (max) v cc . 5v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6 operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 7 operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 8 assumes three state test load (5 pf and a 380 ? thevenin equivalent). 9either t rch or t rrh must be satisfied for a read cycle. 10 t off (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t off is referenced from rising edge of ras or cas , whichever occurs last. 11 t wcs , t wch , t rw d , t cwd and t aw d are not restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t ws t ws (min) and t wh t wh (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. if t rw d t rw d (min), t cwd t cwd (min) and t awd t aw d (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-write cycles. 13 access time is determined by the longest of t caa or t cac or t cpa 14 t asc t cp to achieve t pc (min) and t cpa (max) values. 15 these parameters are sampled and not 100% tested. 16 these characteristics apply to as4c4m4f1 5v devices. ac test conditions key to switching waveforms - access times are measured with output reference levels of v oh = 2.4v and v ol = 0.4v, v ih = 2.4v and v il = 0.8v - input rise and fall times: 2 ns *including scope and jig capacitance 50 pf* r2 = 295 ? r1 = 828 ? d out gnd +3.3v figure a: equivalent output load (as4c4m4f1) undefined output/don?t care falling input rising input
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 8 of 13 ? read waveform early write waveform t ras t rc t rp t rsh t rad t rch t roh t cac t oea t off (see note 11) t oez ras cas address we oe dq column address t crp t csh t rcd t asc t cah t cas t ral t rah t rcs t aa t clz t rrh data out t rac t asr row address t roh t wez t olz t rez t ras t rc t rp t crp t rsh t rcd t csh t cas t rad t asc t cah t wcs t cwl t rw l t wch t wp t ds t dh data in ras cas address we oe dq row address t ral column address t rah t asr
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 9 of 13 ? write waveform oe controlled read-modify-write waveform row address t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t ral t rad t cah t cwl t rwl t oeh t ds t dh data in ras cas address we oe dq column address t wp t asc t asr t oed t ras t rw c t rp t crp t rsh t rcd t csh t cas t rad t ral t ar t cah t cwl t cwd t rw l t aw d t wp t oea t clz t cac t aa t ds t dh row address column address data in data out ras cas address we oe dq t rah t rw d t rcs t rac t oez t oed t asc t asr t olz
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 10 of 13 ? fast page mode read waveform fast page mode byte write waveform row t rasp t rp t crp t rcd t cas t csh t rsh t pc t asr t rad t rch t rcs t rrh t rch t oea t oea t aa t rac t oez t cac data out data out data out column column column ras cas address we oe i/o t ar t rah t asc t cah t ral t rcs t clz t cp t off t cap t rasp t rp t rcd t csh t cas t cp t crp t asr t cah t cah t ral t cah t cwd t aw d t cwd t cwl t cwd t aw d t rwl t wp t oez t oea t rac t ds t clz t cac t cap row column column column data out data in data in data out data out data in ras cas address we oe i/o t rad t rah t rwd t rcs t cwl t oea t aa t dh t ds t clz t cac t clz t cac t oed t pcm
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 11 of 13 ? fast page mode early write waveform cas before ras refresh waveform we = v ih ras only refresh waveform we = oe = v ih or v il t rasp t rwl t asc t wcs t cp t ral t wch t cwl t wp t ds t dh t cas row column column column data in data in data in ras cas address we oe i/o t pc t cah t csh t rcd t oeh t hdr t ar t rad t asr t crp t rah t rsh t oed t rp t rc t ras t rpc t cp t csr t chr ras cas dq open t ras t rp t rc t crp t rpc t asr t rah row address ras address cas
as4c4m4f1 5/22/01; v.1.2 alliance semiconductor p. 12 of 13 ? hidden refresh waveform (read) hidden refresh waveform (write) t ras t rc t rp t ras t rc t rp t crp t rcd t rsh t crp t chr t asr t rad t asc t rrh t oea t clz t cac t oez col address row data out ras cas address we oe dq t ar t rah t rac t aa t rcs t cah t off t ras t rc t rp t crp t rcd t rsh t asr t rah t rad t ar t cah t wcs t wch t ds t dh data in col address row address ras cas address we dq oe t asc t rwl t wcr t wp t dhr t ral t chr
as4c4m4f1 ? 5/22/01; v.1.2 alliance semiconductor p. 13 of 13 ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance res erves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this produc t data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not ass ume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent righ ts, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems w here a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. capacitance 15 ? = 1 mhz, t a = room temperature as4c4m4f1 ordering information as4c4m4f1/f1 family part numbering system parameter symbol signals test conditions max unit input capacitance c in1 a0 to a10 v in = 0v 5 pf c in2 ras , cas , we , oe v in = 0v 7 pf dq capacitance c dq dq0 to dq03 v in = v out = 0v 7 pf package \ ras access time 50 ns 60 ns plastic soj, 300 mil, 24/26-pin 5v AS4C4M4F1-50JC as4c4m4f1-50ji as4c4m4f1-60jc as4c4m4f1-60ji plastic tsop, 300 mil, 24/26-pin 5v as4c4m4f1-50tc as4c4m4f1-50ti as4c4m4f1-60tc as4c4m4f1-60ti as4 c 4m4 f1 ?xx x x dram prefix c = 5v cmos 4m4 f1=2k refresh ras access time package: j = soj 300 mil, 24/26 t = tsop 300 mil, 24/26 temperature range c=commercial, 0c to 70 c i=industrial, -40c to 85c

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